1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a technique for latching address signals in a semiconductor integrated circuit having memory cells.
2. Description of the Related Art
With the development of semiconductor manufacturing technology, a semiconductor integrated circuit has been increasing its operating speed. In particular, microcomputers and the like has been improving in operating frequency year by year, which increases disparity from the operating frequencies of semiconductor memories such as DRAMs.
To narrow this disparity, there have been developed high speed DRAMs including SDRAMs (Synchronous DRAMs) and DDR SDRAMs (Double Data Rate Synchronous DRAMs). SDRAMs perform data transfer from/to exterior in serial, and read/write data from/to memory cells in parallel so as to improve data transmission speed.
Nevertheless, a data bus usage rate decreases during random accesses when the SDRAMs perform read operations and write operations in combination. A drop in data bus usage rate lowers the transmission amount of data per unit time. On this account, it has been difficult for high speed DRAMs such as SDRAMs to be used as, for example, graphics memories which perform frequent random accesses such as image processing.
In the meantime, for the sake of improvement in data bus usage rate, there have recently been proposed SDRAMs having a function called xe2x80x9cdelayed writexe2x80x9d, in which write data supplied in correspondence with a write command is written to memory cells at the time of supplying the next write command.
FIG. 1 shows the operation of a DDR-SDRAM having a delayed write function. In this example, the number of clock cycles from the acceptance of a read command to the output of read data, or a read latency, is set at xe2x80x9c2xe2x80x9d. The number of clock cycles from the acceptance of a write command to the output of write data, or a write latency, is also set at xe2x80x9c2xe2x80x9d.
Initially, in synchronization with a clock signal CLK, read commands RD0, RD1 and read addresses ADR0, ADR1 are successively supplied as a command signal CMD and an address signal ADD, respectively, so that a memory core operates (FIG. 1, (a)). Then, two clocks after the acceptance of the individual read commands RD0 and RD1, read data Q00, Q01, Q10, and Q11 are output in succession as a data signal DQ (FIG. 1, (b)).
Next, two clocks after the acceptance of the read command RD1, a write command WR0 and a write address ADW0 are supplied (FIG. 1, (c)). The write address ADW0 is held in an address resister temporarily. Here, in synchronization with the write command WR0, previous write data held in a data resister is written to the memory core by using a previous write address held in the address register (FIG. 1, (d)).
Write data DA0 and DA1 are supplied two clocks after the write command WR0. That is, the write data DA0 and DA1 are supplied in synchronization with the clock signal CLK after the output of the read data Q11 (FIG. 1, (e)). The write data DA0 and DA1 are held in the data resister temporarily (FIG. 1, (f)).
Then, in synchronization with the clock signal CLK subsequent to the write command WR0, read commands RD2, RD3, and RD4 are supplied in succession, and read operations are carried out (FIG. 1, (g)).
Moreover, two clocks after the acceptance of the read command RD4, a next write command WR1 and write address ADW1 are supplied (FIG. 1, (h)). Input/output circuits and the memory core operate in synchronization with the write command WR1, whereby the write data DA0 and DA1 held in the data register are written to the memory core by using the previous write address signal ADW0 held in the address register (FIG. 1, (i)).
Next, write data DA2 and DA3 are supplied two clocks after the write command WR1. The contents of the data register are rewritten by the write data DA2 and DA3 (FIG. 1, (j)).
As described above, in an SDRAM having a delayed write function, write operations on memory cells are performed at different timing from the accepting timing of write data. This avoids a conflict between the operation of the memory core corresponding to a write command and the operation of the memory core unit corresponding to a read command supplied immediately after the write command. As a result, the data bus usage rate improves as compared to those of ordinary SDRAMs and the amount of data transfer increases. In other words, high speed operations are enabled.
FIG. 2 shows an address latching circuit 1 in the SDRAM having a delayed write function.
This address latching circuit 1 selects either a read address signal RADD supplied from exterior or a write address signal WADD supplied from the address register mentioned above, and outputs the same to an address decoder (not shown).
The address latching circuit 1 has a switching circuit 2 for transmitting the read address RADD, a switching circuit 3 for transmitting the write address WADD, a latch 4 consisting of two inverters, and an inverter 5. The switching circuits 2 and 3 consist of a CMOS transmission gate and an inverter for controlling the pMOS transistor (hereinafter simply referred to as pMOS) in this transmission gate. The switching circuit 2 is controlled by a read clock signal RCLK which is activated in read operations. The switching circuit 3 is controlled by a write clock signal WCLK which is activated in write operations. The latch 4 outputs an internal address signal ADDCX and, through the inverter 5, an internal address signal ADDCZ.
FIG. 3 shows an example of the operation of the address latching circuit 1. Parenthetically, in the following description, some signal names will be referred to in abbreviations such as xe2x80x9cRADD signalxe2x80x9d for xe2x80x9cread address signal RADDxe2x80x9d.
Initially, the RADD signal is supplied to the address latching circuit 1 in a high-level period of the RCLK signal (FIG. 3, (a)). Here, in order to avoid a mislatch, the RADD signal is supplied throughout the high-level period of the RCLK signal. That is, the RADD signal need be supplied to satisfy both a setup time tS for a rising edge of the RCLK signal and a hold time tH for a falling edge of the same. The RADD signal is latched into the latch 4, and output as complementary ADDCZ and ADDCX signals (FIG. 3, (b)).
Moreover, the WADD signal is supplied to the address latching circuit 1 throughout a high-level period of the WCLK signal (FIG. 3, (c)). Likewise, the WADD signal also requires the setup time tS and the hold time tH. The WADD signal is latched into the latch 4 and is output as complementary ADDCZ and ADDCX signals (FIG. 3, (d)).
Now, description will be given of the malfunctions of the address latching circuit 1.
For example, when the RADD signal is changed during a high-level period of the RCLK signal (FIG. 3, (e)), it is impossible for the latch 4 to correctly latch the RADD signal (low level, here) (FIG. 3, (f)). When a hazard arises on the RCLK signal during the latching period of the WADD signal (FIG. 3, (g)), it is also impossible to correctly latch the WADD signal (low level, here) (FIG. 3, (h)). Therefore, an incorrect address signal is supplied to the address decoder. As a result, the memory core receives a correct address signal to start operating, and then receives a different address during the operation, which leads to malfunction. Furthermore, when both the RCLK signal and the WCLK signal are activated simultaneously as shown in FIG. 3(g), a feedthrough current flows due to the conflict between the RADD signal and the WADD signal.
FIG. 4 shows another address latching circuit 6.
This address latching circuit 6 includes a resetting circuit 7 which receives a latch address signal ADDL output from the latch 4 and outputs the address signals ADDCZ and ADDCX. The resetting circuit 7 has NAND gates 7a and 7b to be controlled by a reset signal RESETX. The resetting circuit 7 receives the reset signal RESETX of low level when the memory core is not in operation, and outputs the address signals ADDCZ and ADDCX of high level. Therefore, the address decoder will not be activated in the non-operational period of the memory core. The switching circuits 2, 3, and the latch 4 are identical to those of the address latching circuit 1 shown in FIG. 2.
FIG. 5 shows an example of the operation of the address latching circuit 6.
The individual signals are input at the same timing as that in FIG. 3 (FIG. 5, (a), (c), (e), and (f)). The resetting circuit 7 is activated in high-level periods of the RESETX signal, outputting the settled address signals ADDCZ and ADDCX (FIG. 5, (b) and (d)). The resetting circuit 7 is inactivated in low-level periods of the RESETX signal, outputting the address signals ADDCZ and ADDCX of high level.
Next, description will be given of the malfunctions of the address latching circuit 6.
For example, when the RADD signal is changed during a high-level period of the RCLK signal (FIG. 5, (e)), it is impossible for the latch 4 to latch the RADD signal (low level, here) correctly (FIG. 5, (f)). When a hazard occurs on the RCLK signal during the latching period of the WADD signal (FIG. 5, (g)), it is also impossible to latch the WADD signal (low level, here) correctly (FIG. 5, (h)). Consequently, the memory core malfunctions as in FIG. 3. Moreover, as in FIG. 3, a feedthrough current flows when both the RCLK signal and the WCLK signal are activated at the same time.
As described above, the conventional address latching circuits 1 and 6 might cause malfunction of memory cores depending on the timing where noise occurs.
Besides, the address latching circuits 1 and 6 need the setup times for the rising edges of the RCLK and WCLK signals, and the hold times for the falling edges of the same. Therefore, the latching of address signals requires the address signals to be validated for a long period. This hampers high speed operations.
In particular, SDRAMs having a delayed write function which have been proposed for high speed operation, require to switch address signals in accordance with command inputs from exterior, and operate internal circuits with minimum timing margins. The same holds true for SDRAMs having a plurality of memory cores (banks) independently operating.
Accordingly, it is necessary to minimize the settling period of address signals as possible in order to raise the clock frequency for high speed operations.
An object of the present invention is to provide a semiconductor integrated circuit capable of latching addresses at high speed and with reliability.
According to one of the aspects of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit comprises a latch having two inverting circuits feeding back to each other and a supply connecting circuit. The supply connecting circuit selects one input signal from a plurality of input signals corresponding to a plurality of select signals in response to the activation of any one of the select signals. The supply connecting circuit connects a supply to either of the inverting circuits in the latch depending on the input signal selected. The latch is forced to be unbalanced due to the activation of one inverting circuit so as to latch a value corresponding to the input signal selected by the select signal.
A value to be latched is determined with the states of the input signals supplied at the activation of a select signal. This minimizes the settling periods of the input signals with respect to the select signals. As a result,the timing margins of the circuit increase, thereby realizing high speed operations. Logics of the input signals are indirectly latched by connecting the supply to either of the inverting circuits for activation. This precludes the inversion of latched values, even if the select signals or the input signals change due to noises or other reasons after the latch latching the signals. In other words, the latch is prevented from malfunctioning due to noises or the like.
According to another aspect of the semiconductor integrated circuit in the present invention, a resetting circuit resets the latch upon the inactivation of all of the select signals. Complementary output signals output from the latch have same logic level owing to the resetting. This facilitates the inactivation of circuits that receive the outputs of the latch.
According to another aspect of the semiconductor integrated circuit in the present invention, the supply connecting circuit keeps connecting the supply to the inverting circuit in response to the output of the latch which is in a predetermined state upon receipt of the state of the input signal. Accordingly, the state of the latch is held uninverted thereafter even when the input signal changes. The latch is prevented from malfunctioning due to noises or the like occurring in the input signals.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit comprises a plurality of memory cells, a control circuit, and an address register. The control circuit generates a write control signal or a read control signal as the select signal in accordance with a command signal supplied from an exterior. The address register holds a write address signal supplied from the exterior in correspondence with the command signal indicating a write operation. The latch latches, as the input signal, one of the write address signal for a previous write operation output from the address register in synchronization with the write control signal, and a read address signal supplied from the exterior in synchronization with the read control signal. That is, it is possible to switch address signals for read operations and address signals for write operations at high speed in the semiconductor integrated circuit having a delayed write function for performing a write operation on memory cells by using write address held in the address register.